#static pin constraints
set_property IOSTANDARD LVCMOS18 [get_ports pin_fpga_act_led]
set_property IOSTANDARD LVCMOS18 [get_ports pin_opt0_lnk_led]
set_property IOSTANDARD LVCMOS18 [get_ports pin_opt1_lnk_led]
set_property IOSTANDARD LVCMOS18 [get_ports pin_fpga2e2p_i2c_wp]
set_property IOSTANDARD LVCMOS18 [get_ports pin_fpga2e2p_i2c_scl]
set_property IOSTANDARD LVCMOS18 [get_ports pin_fpga2e2p_i2c_sda]
set_property IOSTANDARD LVCMOS18 [get_ports pin_fpga2mcu_i2c_scl]
set_property IOSTANDARD LVCMOS18 [get_ports pin_fpga2mcu_i2c_sda]
set_property IOSTANDARD LVCMOS18 [get_ports pin_fpga2mcu_rsv0]
set_property IOSTANDARD LVCMOS18 [get_ports pin_fpga2mcu_rsv1]
set_property IOSTANDARD LVCMOS18 [get_ports pin_mcu2fpga_i2c_scl]
set_property IOSTANDARD LVCMOS18 [get_ports pin_mcu2fpga_i2c_sda]
set_property IOSTANDARD LVCMOS18 [get_ports pin_opt0_act_led]
set_property IOSTANDARD LVCMOS18 [get_ports pin_opt1_act_led]
set_property IOSTANDARD LVCMOS18 [get_ports pin_sta_secure_rst_n]
set_property IOSTANDARD LVCMOS18 [get_ports pin_sta_secure_scl]
set_property IOSTANDARD LVCMOS18 [get_ports pin_sta_secure_sda]
set_property IOSTANDARD LVCMOS18 [get_ports pin_dync_secure_rst_n]
set_property IOSTANDARD LVCMOS18 [get_ports pin_dync_secure_scl]
set_property IOSTANDARD LVCMOS18 [get_ports pin_dync_secure_sda]
set_property IOSTANDARD LVCMOS18 [get_ports pin_reset_n]
set_property IOSTANDARD LVDS [get_ports pin_sys_clk_p]
set_property IOSTANDARD LVCMOS18 [get_ports pin_opt0_25g_mod_abs_def0]
set_property IOSTANDARD LVCMOS18 [get_ports pin_opt0_25g_rx_los0]
set_property IOSTANDARD LVCMOS18 [get_ports pin_opt0_25g_tx_dis0]
set_property IOSTANDARD LVCMOS18 [get_ports pin_opt1_25g_mod_abs_def0]
set_property IOSTANDARD LVCMOS18 [get_ports pin_opt1_25g_rx_los0]
set_property IOSTANDARD LVCMOS18 [get_ports pin_opt1_25g_tx_dis0]
set_property IOSTANDARD LVCMOS18 [get_ports pin_program_inband]
######################################################################################################################
## 100MHz system clk
set_property DIFF_TERM_ADV TERM_100 [get_ports pin_sys_clk_p]
######################################################################################################################
set_property PACKAGE_PIN BB23 [get_ports pin_fpga2e2p_i2c_wp]
set_property PACKAGE_PIN BE24 [get_ports pin_fpga2e2p_i2c_scl]
set_property PACKAGE_PIN BE23 [get_ports pin_fpga2e2p_i2c_sda]
set_property PACKAGE_PIN BE22 [get_ports pin_fpga2mcu_i2c_scl]
set_property PACKAGE_PIN BD23 [get_ports pin_fpga2mcu_i2c_sda]
set_property PACKAGE_PIN BA22 [get_ports pin_fpga2mcu_rsv0]
set_property PACKAGE_PIN BA24 [get_ports pin_fpga2mcu_rsv1]
set_property PACKAGE_PIN BC23 [get_ports pin_fpga_act_led]
set_property PACKAGE_PIN AY24 [get_ports pin_reset_n]
set_property PACKAGE_PIN BD22 [get_ports pin_mcu2fpga_i2c_scl]
set_property PACKAGE_PIN BD21 [get_ports pin_mcu2fpga_i2c_sda]
set_property PACKAGE_PIN BA25 [get_ports pin_opt0_25g_mod_abs_def0]
set_property PACKAGE_PIN BF22 [get_ports pin_opt0_25g_rx_los0]
set_property PACKAGE_PIN BF24 [get_ports pin_opt0_25g_tx_dis0]
set_property PACKAGE_PIN BB22 [get_ports pin_opt0_act_led]
set_property PACKAGE_PIN BB21 [get_ports pin_opt1_lnk_led]
set_property PACKAGE_PIN AT24 [get_ports pin_opt1_25g_mod_abs_def0]
set_property PACKAGE_PIN AY23 [get_ports pin_opt1_25g_rx_los0]
set_property PACKAGE_PIN AY22 [get_ports pin_opt1_25g_tx_dis0]
set_property PACKAGE_PIN AP23 [get_ports pin_opt1_act_led]
set_property PACKAGE_PIN AL8 [get_ports pin_pcie_ref_clk_n]
set_property PACKAGE_PIN AL9 [get_ports pin_pcie_ref_clk_p]
set_property PACKAGE_PIN AA3 [get_ports {pin_pcie_rxn_in[0]}]
set_property PACKAGE_PIN AA4 [get_ports {pin_pcie_rxp_in[0]}]
set_property PACKAGE_PIN Y6 [get_ports {pin_pcie_txn_out[0]}]
set_property PACKAGE_PIN Y7 [get_ports {pin_pcie_txp_out[0]}]
set_property PACKAGE_PIN AB1 [get_ports {pin_pcie_rxn_in[1]}]
set_property PACKAGE_PIN AB2 [get_ports {pin_pcie_rxp_in[1]}]
set_property PACKAGE_PIN AB6 [get_ports {pin_pcie_txn_out[1]}]
set_property PACKAGE_PIN AB7 [get_ports {pin_pcie_txp_out[1]}]
set_property PACKAGE_PIN AC3 [get_ports {pin_pcie_rxn_in[2]}]
set_property PACKAGE_PIN AC4 [get_ports {pin_pcie_rxp_in[2]}]
set_property PACKAGE_PIN AD6 [get_ports {pin_pcie_txn_out[2]}]
set_property PACKAGE_PIN AD7 [get_ports {pin_pcie_txp_out[2]}]
set_property PACKAGE_PIN AD1 [get_ports {pin_pcie_rxn_in[3]}]
set_property PACKAGE_PIN AD2 [get_ports {pin_pcie_rxp_in[3]}]
set_property PACKAGE_PIN AF6 [get_ports {pin_pcie_txn_out[3]}]
set_property PACKAGE_PIN AF7 [get_ports {pin_pcie_txp_out[3]}]
set_property PACKAGE_PIN AE3 [get_ports {pin_pcie_rxn_in[4]}]
set_property PACKAGE_PIN AE4 [get_ports {pin_pcie_rxp_in[4]}]
set_property PACKAGE_PIN AH6 [get_ports {pin_pcie_txn_out[4]}]
set_property PACKAGE_PIN AH7 [get_ports {pin_pcie_txp_out[4]}]
set_property PACKAGE_PIN AF1 [get_ports {pin_pcie_rxn_in[5]}]
set_property PACKAGE_PIN AF2 [get_ports {pin_pcie_rxp_in[5]}]
set_property PACKAGE_PIN AK6 [get_ports {pin_pcie_txn_out[5]}]
set_property PACKAGE_PIN AK7 [get_ports {pin_pcie_txp_out[5]}]
set_property PACKAGE_PIN AG3 [get_ports {pin_pcie_rxn_in[6]}]
set_property PACKAGE_PIN AG4 [get_ports {pin_pcie_rxp_in[6]}]
set_property PACKAGE_PIN AM6 [get_ports {pin_pcie_txn_out[6]}]
set_property PACKAGE_PIN AM7 [get_ports {pin_pcie_txp_out[6]}]
set_property PACKAGE_PIN AH1 [get_ports {pin_pcie_rxn_in[7]}]
set_property PACKAGE_PIN AH2 [get_ports {pin_pcie_rxp_in[7]}]
set_property PACKAGE_PIN AN4 [get_ports {pin_pcie_txn_out[7]}]
set_property PACKAGE_PIN AN5 [get_ports {pin_pcie_txp_out[7]}]
set_property PACKAGE_PIN AJ3 [get_ports {pin_pcie_rxn_in[8]}]
set_property PACKAGE_PIN AJ4 [get_ports {pin_pcie_rxp_in[8]}]
set_property PACKAGE_PIN AP6 [get_ports {pin_pcie_txn_out[8]}]
set_property PACKAGE_PIN AP7 [get_ports {pin_pcie_txp_out[8]}]
set_property PACKAGE_PIN AK1 [get_ports {pin_pcie_rxn_in[9]}]
set_property PACKAGE_PIN AK2 [get_ports {pin_pcie_rxp_in[9]}]
set_property PACKAGE_PIN AR4 [get_ports {pin_pcie_txn_out[9]}]
set_property PACKAGE_PIN AR5 [get_ports {pin_pcie_txp_out[9]}]
set_property PACKAGE_PIN AM1 [get_ports {pin_pcie_rxn_in[10]}]
set_property PACKAGE_PIN AM2 [get_ports {pin_pcie_rxp_in[10]}]
set_property PACKAGE_PIN AT6 [get_ports {pin_pcie_txn_out[10]}]
set_property PACKAGE_PIN AT7 [get_ports {pin_pcie_txp_out[10]}]
set_property PACKAGE_PIN AP1 [get_ports {pin_pcie_rxn_in[11]}]
set_property PACKAGE_PIN AP2 [get_ports {pin_pcie_rxp_in[11]}]
set_property PACKAGE_PIN AU4 [get_ports {pin_pcie_txn_out[11]}]
set_property PACKAGE_PIN AU5 [get_ports {pin_pcie_txp_out[11]}]
set_property PACKAGE_PIN AT1 [get_ports {pin_pcie_rxn_in[12]}]
set_property PACKAGE_PIN AT2 [get_ports {pin_pcie_rxp_in[12]}]
set_property PACKAGE_PIN AW4 [get_ports {pin_pcie_txn_out[12]}]
set_property PACKAGE_PIN AW5 [get_ports {pin_pcie_txp_out[12]}]
set_property PACKAGE_PIN AV1 [get_ports {pin_pcie_rxn_in[13]}]
set_property PACKAGE_PIN AV2 [get_ports {pin_pcie_rxp_in[13]}]
set_property PACKAGE_PIN BA4 [get_ports {pin_pcie_txn_out[13]}]
set_property PACKAGE_PIN BA5 [get_ports {pin_pcie_txp_out[13]}]
set_property PACKAGE_PIN AY1 [get_ports {pin_pcie_rxn_in[14]}]
set_property PACKAGE_PIN AY2 [get_ports {pin_pcie_rxp_in[14]}]
set_property PACKAGE_PIN BC4 [get_ports {pin_pcie_txn_out[14]}]
set_property PACKAGE_PIN BC5 [get_ports {pin_pcie_txp_out[14]}]
set_property PACKAGE_PIN BB1 [get_ports {pin_pcie_rxn_in[15]}]
set_property PACKAGE_PIN BB2 [get_ports {pin_pcie_rxp_in[15]}]
set_property PACKAGE_PIN BE4 [get_ports {pin_pcie_txn_out[15]}]
set_property PACKAGE_PIN BE5 [get_ports {pin_pcie_txp_out[15]}]
set_property PACKAGE_PIN BC21 [get_ports pin_program_inband]
set_property PACKAGE_PIN AU24 [get_ports pin_sta_secure_rst_n]
set_property PACKAGE_PIN AR22 [get_ports pin_sta_secure_scl]
set_property PACKAGE_PIN AR24 [get_ports pin_sta_secure_sda]
set_property PACKAGE_PIN H25 [get_ports pin_dync_secure_rst_n]
set_property PACKAGE_PIN A25 [get_ports pin_dync_secure_scl]
set_property PACKAGE_PIN J25 [get_ports pin_dync_secure_sda]
set_property PACKAGE_PIN AW22 [get_ports pin_sys_clk_n]
set_property PACKAGE_PIN AW23 [get_ports pin_sys_clk_p]
######################################################################################################################
#DDR bank Vref setting
#dync bank Vref setting
set_property INTERNAL_VREF 0.9 [get_iobanks 53]
#static bank Vref setting
set_property INTERNAL_VREF 0.9 [get_iobanks 64]
set_property INTERNAL_VREF 0.6 [get_iobanks 65]

######################################################################################################################
#timing constraints
#sys ref clk 100M
create_clock -period 10.000 -name pin_sys_clk_p [get_ports pin_sys_clk_p]
create_clock -period 10.000 -name pin_pcie_ref_clk_p [get_ports pin_pcie_ref_clk_p]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets u_clkm_top/u_clkm/u_mmcm_sys/inst/clk_out1]
create_generated_clock -name mmcm_sysclk_out0 [get_pins u_clkm_top/u_clkm/u_mmcm_sys/inst/mmcme4_adv_inst/CLKOUT0]
######################################################################################################################
set_clock_groups -asynchronous -group [get_clocks pin_sys_clk_p]
set_clock_groups -asynchronous -group [get_clocks mmcm_sysclk_out0]
set_false_path -from [get_clocks pin_pcie_ref_clk_p] -to [get_clocks mmcm_sysclk_out0]

set_multicycle_path -setup -to [get_pins hpi_cpu_data_out_reg*/D] 2
set_multicycle_path -hold -to [get_pins hpi_cpu_data_out_reg*/D] 1
######################################################################################################################
#jitter constraints
set_input_jitter pin_pcie_ref_clk_p 0.100
# ####################################################################################################################
## Vref setting
set_property INTERNAL_VREF 0.75 [get_iobanks 44]
# ####################################################################################################################
#bitstream gen cfg for spi interface
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 21.3 [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_pins u_clkm_top/u_clkm/u_clk_100m_sys_bufg/O]
######################################################################################################################
set_max_delay -datapath_only -from [get_cells -hier *spi_sck_reg] -to [get_pins -hier *STARTUP*_inst/USRCCLKO] 2.000
set_max_delay -datapath_only -from [get_cells -hier *spi_mosi_reg] -to [get_pins -hier {*STARTUP*_inst/DO[0]}] 2.000
set_max_delay -datapath_only -from [get_pins -hier {*STARTUP*_inst/DI[1]}] -to [get_cells -hier {*rx_data_buf_sft_reg[0]}] 2.000
####################################################################################
# Constraints from file : 'pcie_sriov_x16_late.xdc'
####################################################################################
set_property PACKAGE_PIN AN24 [get_ports pin_opt0_lnk_led]

